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rev. 1.0 january 2013 www.aosmd.com page 1 of 15 AOZ7111 critical conduction mode pfc controller general description the AOZ7111 is an active power factor correction (pfc) controller for boost pfc applications that operate in critical conduction mode (crm). the device uses a voltage mode pwm which does not need rectified ac line voltage information, it saves the power loss of an input sensing network necessary for traditional current- mode crm pfc controller. the AOZ7111 minimizes the number of external components by integrating safety features that make it an excellent choice for designing robust pfc stages. the AOZ7111 is available in a so-8 package and it is rated over a -40c to +125c ambient temperature range. features ? no ac input voltage sensing requirement ? ac fault detect? makes system more robust ? maximum switching fr equency limitation ? additional ovp detection pin ? output over-voltage / open-feedback protection and disable function ? internal closed loop soft-start ? dynamic ovp function ? non-linear gain error amplifier enable fast line and load transient response ? no need for the auxiliary winding with minus current detection (zcd) ? 150s internal start-up timer ? mosfet over-current protection and inductor saturation protection ? under-voltage lockout with hysteresis ? lower startup and operating current ? +300ma / -800ma peak gate drive current ? thermal shutdown ? so-8 package applications ? adapter / ballast ? lcd tv / led tv ? smps typical application ovp gnd out inv ct vcc comp cs AOZ7111 + vcc ac line filter vout + figure 1. typical boost pfc application
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 2 of 15 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/media/ aosgreenpolicy.pdf for additional information. pin configuration pin description part number ambient temperature range package environmental AOZ7111ai -40c to +125c so-8 green product pin number pin name pin function 1 inv inverting input of the error amplifier. the out put voltage of the boost pfc converter should be resistively divided to 2.5v. 2 ct the ct pin sources a current to charge an exte rnal timing capacitor. the circuit controls the power switch on time by comparing the ct vo ltage to an internal voltage derived from v comp . the ct pin discharge the external timing capacitor at the end of the on time. 3 comp this pin is the output of the transcon ductance error amplifie r. components for the compensation should be connected between this pin and gnd. 4 ovp the ovp pin is used to detect pfc output over-voltage when the inv pin information is not correct. 5 cs this pin is the input of the zero current detection and over-current protection comparator. 6 gnd the gnd pin is analog ground. 7 out this pin is the gate drive output. 8 vcc this is the ic supply pin. 1 2 3 4 inv ct comp ovp so-8 (top view) vcc out gnd cs 8 7 6 5
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 3 of 15 absolute maximum ratings exceeding the absolute maximum ratings may damage the device. symbol parameter min max units v cc supply voltage -0.3 20 v i oh , i ol peak drive output current -800 +300 ma i clamp driver output clamping diode vo>vcc or vo<-0.3v -10 +10 ma v in inv, ovp pin input voltage -0.3 5 v ct, comp pin input voltage -0.3 9.5 v cs pin input voltage -5 0.3 v driver output voltage -0.3 v cc v t j operating junction temperature +150 c t a operating temperature range -40 +125 c t s storage temperature range -65 +150 c esd electrostatic discharge capability (human body model, jes22-a114) 2.5 kv t l lead temperature (soldering, 10s) 300 c ? ja package thermal resistance (junction-to-ambient) 150 c/w electrical characteristics t a = 25c, v cc = 14v, unless otherwise specified (1) symbol parameter conditions min typ max units supply v cc operating range after turn on 10.5 18 v v start start threshold voltage v cc increasing 11 12 13 v v stop stop threshold voltage v cc decreasing 8.5 9.5 10.5 v v uvlo_hy input under-voltage lockout hysteresis 2.5 v v z zener voltage i cc = 20ma 18 20 22 v i in_ns non-switching supply current v comp < 0.9v, v in = 14v 0.5 1.0 1.5 ma i stb standby current v inv < 0.2v 30 60 a error amplifier v ref voltage reference t j = 25c 2.465 2.5 2.535 v v ref_line line regulation v cc = 14v ~ 18v 10 mv g m transconductance v inv = 2.4v to 2.6v 75 100 125 s i o error amplifier current capability source: v inv = v ref -0.1v sink: v inv = v ref +0.1v -10 +10 a c t_offset minimum control voltage to generate drive pluses 1.0 v ramp oscillator f max maximum oscillating frequency 350 khz t start restart timer delay 50 150 300 s v ct(max) ct peak voltage v comp = open 8 v i charge on time capacitor charge current 150 200 250 a
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 4 of 15 note: 1. specifications in bold indicate an ambient temperature range -40c to +125c. these specificati ons are guaranteed by design. zero current detection v zcd-th zero current detection comparator threshold -24 -15 -9 mv v ocp1 ocp1 threshold voltage (shutdown mode) -0.8 -0.7 -0.6 v v ocp2 ocp2 threshold voltage (latch mode) -1.2 v t zcd, d output delay from zcd to output turn-on 650 ns gate drive r oh drive pull-up resistance i source = 50ma 24 30 ? r ol drive pull-down resistance i sink = 50ma 5 6 ? t rise output rise time c l = 1nf, 10% to 90% 70 ns t fall output fall time c l = 1nf, 90% to 10% 25 ns protection v dovp dynamic ovp threshold voltage t a = 25c 2.54 2.575 2.61 v hv ovp_inv dynamic ovp hysteresis t a = 25c 0.05 v v ovp_inv ovp threshold voltage @ inv pin t a = 25c 2.62 2.685 2.75 v hv ovp_inv ovp hysteresis @ inv pin t a = 25c 0.175 v v ovp ovp threshold voltage @ ovp pin t a = 25c 2.65 2.75 2.85 v v en_inv inv enable threshold t a = 25c 0.5 v hy en inv enable hysteresis t a = 25c 0.01 0.055 0.120 v otp over-temperature shutdown limit t j rising t j falling 150 100 c t hys hysteresis temperature of otp 50 c electrical characteristics (continued) t a = 25c, v cc = 14v, unless otherwise specified (1) symbol parameter conditions min typ max units
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 5 of 15 functional block diagram gnd ovp vcc inv out delay internal +5v uvlo & por ramp control reference & bias 2.5v eamp + ? + ? dynamic ovp 100s + ? comp 2.575v + ? ct -15mv + ? zcd cs leb + ? -0.7v restart timer s r q fmax limit ac input fault detect 2.685v + ? s r por q gate driver 2.75v vz drv 1 st ovp ocp
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 6 of 15 typical characteristics charge current vs. temperature temperature (c) 250 240 230 220 210 200 190 180 170 160 150 -150 -25 0 25 50 75 100 125 charge current (a) start threshold vs. temperature temperature (c) 13.0 12.8 12.6 12.4 12.2 12.0 11.8 11.6 11.4 11.2 11.0 -150 -25 0 25 50 75 100 125 start threshold (v) stop threshold vs. temperature temperature (c) 10.5 10.3 10.1 9.9 9.7 9.5 9.3 9.1 8.9 8.7 8.5 -150 -25 0 25 50 75 100 125 stop threshold (v) opc1 vs. temperature temperature (c) -0.60 -0.62 -0.64 -0.66 -0.68 -0.70 -0.72 -0.74 -0.76 -0.78 -0.80 -150 -25 0 25 50 75 100 125 opc1 (v) ovp vs. temperature temperature (c) 2.85 2.80 2.75 2.70 2.65 -150 -25 0 25 50 75 100 125 ovp (v) ovp_inv vs. temperature temperature (c) 2.72 2.70 2.68 2.66 2.64 2.62 -150 -25 0 25 50 75 100 125 ovp_inv (v)
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 7 of 15 typical characteristics (continued) en_inv vs. temperature temperature (c) 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 -150 -25 0 25 50 75 100 125 en_inv (v) reference vs. temperature temperature (c) 2.535 2.525 2.515 2.505 2.495 2.485 2.475 2.465 -150 -25 0 25 50 75 100 125 reference (v) max frequency vs. temperature temperature (c) 400 390 380 370 360 350 340 330 320 310 300 -150 -25 0 25 50 75 100 125 max frequency (khz) restart timer delay vs. temperature temperature (c) 300 250 200 150 100 50 -150 -25 0 25 50 75 100 125 restart timer delay (s) output delay vs. temperature temperature (c) 900 850 800 750 700 650 600 -150 -25 0 25 50 75 100 125 output delay (ns) zcd comparator threshold vs. temperature temperature (c) -8 -10 -12 -14 -16 -18 -20 -22 -24 -150 -25 0 25 50 75 100 125 zcd comparator threshold (mv)
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 8 of 15 detailed description the AOZ7111 is a voltage mode active power factor correction (pfc) controller de signed for cost-effective boost pfc applications that operate in critical conduction mode (crm). its voltage mode scheme does not require an ac input line-sensing network, usually necessary for a current mode crm pfc controller. it gets the zcd signal pulse from the current sense resistor; therefore, zcd auxiliary winding is not needed. AOZ7111 features output over-voltage protection, over- current protection, open-feedback protection, and under- voltage lockout protection. a unique ac input fault detection circuit makes the sy stem more robust during the ac absent test. the additional ovp pin can be used to double check the output voltage if the feedback resistor gets damaged. the controller also implements comprehensive safety features for robust designs. the AOZ7111 is available in so-8 package. error amplifier regulation AOZ7111 regulates the boost output voltage using an internal transconductance error amplifier (ea) with a typical transconductance value of 100s. the advantage in using a transconductance error amplifier is that the inv pin voltage is only determined by the resistor divider network connected to the output voltage, not the operation of the amplifier. this enables the inv pin to be used for sensing over-v oltage or under-voltage conditions independently of the error amplifier. the negative terminal of the ea is pinned out to inv, the positive terminal is connected to a 2.5v (1.8%) reference (v ref ), and the ea output is pinned out comp. the output of the error amplifier (comp) is connected to the pwm comparator and controls the on-time of the out output. the sink and source current capability of the error amplifier is approximate 10a during normal operation. when the inv pin voltage is over the normal operating conditions (v inv >2.6v, or v inv <2.4v if the error is large), additional circuitry is activa ted to enhance the slew-rate of the error amplifier, it enables fast line and load transient response. figure 2. non-linear gain characteristics the output voltage of pfc contains a high ripple frequency, 2 times the ac power line (50hz or 60hz). the v out ripple is attenuated by the regulation loop to ensure v comp is constant during the ac line cycle. in order to obtain a stable operation and ensure v comp is constant during the ac line cycle, the bandwidth should typically be set below 20hz so that the regulation block output may be relatively constant over a given ac line cycle. soft-start AOZ7111 employs an internal soft-start function to suppress inrush current and overshoot of output voltage during the startup. the soft-start circuit works after uvlo and standby are released and before the soft-start cancellation voltage is exceeded. during the soft-start, the ota supplies a constant 10a into the compensation network at the comp pin. the voltage at this pin rises linearly as well as the amplitude of the input current. as soon as the output voltage v out reaches 95% of its rated level, the startup procedure is finished and the normal voltage control takes over. 100s i comp inv 2.4v 2.6v 2.5v source sink 200s
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 9 of 15 figure 3. soft-start sequence on time control (ramp control oscillator) the switching pattern consists of constant on times and variable off times for a given rms input voltage and output load. the AOZ7111 controls the on-time with the capacitor connected to the ct pin. a current source charges the ct capacitor to a voltage derived from the comp pin voltage (v ct(off) ). v ct(off) is calculated as below: when v ct(off) is reached, the drive turns off. the ramp oscillator cons ists of three phases: charge phase: the oscillator capacitor voltage grows linearly from its bottom valu e (ground) until it exceeds v comp - ct (offset) . at that moment, the pwm latch output gets low and the oscillator discharge sequence is set. discharge phase: the oscillator capacitor is discharged down to its valle y value of 0v. standby phase: at the end of the discharge sequence, the oscillator voltage is mainta ined in a low state until the pwm latch is set again. v comp varies with the rms input voltage and output load, the on time is constant during the ac line cycle if the values of the compensation components are sufficient to filter out the v out ripple. the maximum on time of the controller occurs when v comp is at the maximum. the ct capacitor is sized to ensure that the required on time is reached at maximum output power and the minimum input voltage condition. the minimum ct value is calculated as below: current detection block the current detection circuit is composed of zero current detection and over-current detection. the inductor current is converted into a voltage by inserting a ground reference resistor (r cs ) series with the input diode bridge and the input filtering capacitor. therefore, a negative voltage proportional to the inductor current is built: where, l is the inductor current; r cs is the current sense resistor; v cs is the measured voltage. zero current detection the zero current detection function guarantees that the mosfet can not turn on as long as the inductor current has not reached zero. the negative signal v cs is applied to the current sense at pin 5. the pin 5 voltage is compared to the -15mv threshold so that as long as v cs is lower than this threshold, the current sense comparator resets the pwm latch to force the gate drive signal low state. consequently, it is not possible to turn on the power mosfet until the inductor current is measured smaller than (15mv/r cs ), nearly at zero. v ct off ?? v comp c t offset ?? ? 2 p out li ch e arg ? ? ? eff v ac 2 c t ? ? ---------------------------------------------------------------- - == ct min ?? 2 p out li ch e arg ? ? ? eff v ac 2 v ct max ?? ? ? -------------------------------------------------------------- = v cs r ? cs i l ? = v comp t i ds v out t rated output 95% rated
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 10 of 15 figure 4. switching and current sense operation over-current protection the over-current detection pr otective circuit detects the inductor current and protects the power mosfet by turning off the output driver when it becomes higher than the set current level. with the over-current detection, the voltage across the current detection resistance r cs connected to the gnd is fed to the cs pin. if the cs pin voltage compared by the over-current detection comparator becomes lower than -0.7v, it is then regarded as over-current state; therefore, the feed-forward of the output driver is reset to turn off the power mosfet. restart timer AOZ7111 utilizes self-oscillation instead of the oscillator with fixed frequency. in steady operation, it turns on the mosfet with a signal from the zero current detector. in startup or light load conditions, a trigger signal is required for starting up or stable operation. when the output of the ic continues turn-off (150s or more), the restart trigger signal is automatically generated. maximum switching frequency limit because the mosfet turn-on depends on the cs input, switching frequency may increase to higher than several mhz due to the mis-triggering or noise on the nearby cs pin. if the switching frequency is higher than needed for critical conduction mode, it will enter ccm. in ccm, inductor current can be raised very high, which may exceed the current rating of the power switch or diode. this can seriously damage the power switch and burn it down. to avoid this, the maximum switching frequency limitation is embedded. if the zcd signal is applied again within 2.9s after the previous edge of gate signal, this signal is ignored and AOZ7111 waits for another zcd signal. overvoltage protection (ovp) it is critical that over voltage protection (ovp) prevents the output voltage exceeding the ratings of pfc stage components. over-voltage protection (ovp) is embedded by the information at the inv pin. that information comes from the output through the voltage dividing resistors. AOZ7111 has dynamic ovp function to narrow the on time when the inv voltage is higher than 2.575v. when the voltage further rises and exceeds the comparator reference voltage of static ovp (2.685v), the ovp comparator shuts down the output drive pulse. the ovp logic includes hysteresis to ensure that output voltage has sufficient time to discharge before the AOZ7111 driver recovery and also to ensure noise immunity. additional ovp detection over-voltage protection (ovp) is embedded by the information at the inv pin. that information comes from the output through the voltage dividing resistors. when the upper divider resistor gets damaged and resistance becomes too high the output electrolytic capacitor may explode. to prevent such a catastrophe the additional ovp pin is assigned to double check output voltage. when the second ovp triggers, switching can be recovered only when the v cc supply voltage falls below v stop and builds up higher than uvlo again. -15mv zcd cs t out t ramp+ offset t il t v comp
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 11 of 15 figure 5. ovp circuitry around inv and ovp pin ac input fault detection AOZ7111 does not require an ac input voltage sensing, nor does it need the auxiliary winding with minus current detection. in general, the v cc of pfc controller is supplied by a system standby power supply, a mismatch may occur in a worst case scenario. a worst case scenario could be ac input chattering: the electric ac power source is suddenly absent for two or three additional ac line cycles, v cc is still higher than uvlo (v stop ) during this time, so the voltage control loop tries to compensate for the v out drop and v comp will increase until it reaches its maximum clamp level. during the ac input recovery, high comp leads to very high switching current and severe stress is put on both the mosfet and boost diode. to ensure that the system is more robust and reliable, AOZ7111 has a unique ac input fault detection circuit to protect against this type of scenario. if the ac input voltage is absent two or three additional cycles, internal soft-start is reset and waits for the ac input recovery again. during the ac input recovery, soft-start manages turn-on time allowing the switching current to increase smoothly. figure 6. operation with ac input fault detection under voltage lock out (uvlo) uvlo function is used to prevent controller malfunction when v cc supply voltage drops. when v cc supply voltage reaches 12v (typ), the internal block of the ic is enabled and starts operation. when v cc supply voltage drops below 9.5v (typ), most of the internal circuit is disabled to reduce the ic current consumption. under voltage protection (uvp) AOZ7111 detects the under voltage fault if v inv is less than v en_inv . the uvp comparator disables the operation when v inv is less than 0.5v and there is 55mv hysteresis. an external small-signal mosfet can be used to disables the ic. during disable mode, the current consumption of the ic decreases to 60a or less. v comp i ds t t t v out v ac r ovp1 r ovp2 r fb1 r fb2 + 1.07*v ref + s q r por inv pin ovp pin v out 1.1*v ref
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 12 of 15 application information alpha and omega semiconductor provides an excel based design tool, an application note and a demonstration board to help the design of AOZ7111 and reduce the r&d cycle time. all the tools can be download from: www.aosmd.com . pcb layout guide the following are good pcb layout guideline for a pfc stage: 1. to keep the ic gnd pin as clean as possible, the power stage ground and the signal ground must be separated. 2. the pfc mosfet gate drive loop path should be minimized. 3. minimize the trace lengt h to inv pin. since the feedback node is high impedance the trace from the output resistor divider to inv pin should be as short as possible. 4. switching current sense (cs pin) is very important for the stable operation of pfc stage. normally, a rc filter is recommended to reduce the noise applied to the cs pin. 5. the v cc decoupling capacitor c vcc need to be placed close to ic v cc and gnd pin as much as possible. figure 7. recomme nded pcb layout
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 13 of 15 package dimensions, so-8l notes: 1. all dimensions are in millimeters. 2. dimensions are inclusive of plating. 3. package body size exclude mold flash and gate burrs. mold flash at the non-lead sides should be less than 6 mils each. 4. dimension l is measured in gauge plane. 5. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. symbols a a1 a2 b c d e e e1 h l dimensions in millimeters recommended land pattern min. 1.35 0.10 1.25 0.31 0.17 4.80 3.80 5.80 0.25 0.40 0 unit: mm nom. 1.65 ? 1.50 ? ? 4.90 3.90 1.27 bsc 6.00 ? ? ? max. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8 dimensions in inches h x 45 l c 7 (4x) 2.20 2.87 5.74 1.27 0.80 0.635 b a1 a2 a symbols a a1 a2 b c d e e e1 h l min. 0.053 0.004 0.049 0.012 0.007 0.189 0.150 0.228 0.010 0.016 0 nom. 0.065 ? 0.059 ? ? 0.193 0.154 0.050 bsc 0.236 ? ? ? max. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 0.244 0.020 0.050 8 e1 e d e 1 8 0.25mm gauge plane seating plane 0.10mm
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 14 of 15 tape and reel dimensions, so-8l carrier tape reel tape size 12mm reel size ?330 m ?330.00 0.50 package so-8 (12mm) a0 6.40 0.10 b0 5.20 0.10 k0 2.10 0.10 d0 1.60 0.10 d1 1.50 0.10 e 12.00 0.10 e1 1.75 0.10 e2 5.50 0.10 p0 8.00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.25 0.10 n ?97.00 0.10 k0 unit: mm b0 g m w1 s k h n w v r trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets a0 p1 p2 feeding direction p0 e2 e1 e d0 t d1 w 13.00 0.30 w1 17.40 1.00 h ?13.00 +0.50/-0.20 k 10.60 s 2.00 0.50 g ? r ? v ? leader/trailer and orientation unit: mm
AOZ7111 rev. 1.0 january 2013 www.aosmd.com page 15 of 15 part marking z7111ai fay part number code assembly lot code year & week code wlt fab & assembly location AOZ7111ai (so-8) as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. legal disclaimer alpha and omega semiconductor makes no representation s or warranties with respect to the accuracy or completeness of the information provided herein and takes no liabilities for the consequences of use of such information or any product described herein. alpha and om ega semiconductor reserves the right to make changes to such information at any time without further notice. this document does not constitute the grant of any intellectual property rights or representation of non-infringement of any third party?s intellectual property rights. life support policy alpha and omega semiconductor products are not authorized for use as critical components in life support devices or systems.

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